Many integrated circuits are now fabricated with at least one read/write memory element that is capable of reading and writing data, such as a Random Access Memory (RAM), a Content Addressable Memory (CAM), a First-In, First-Out (FIFO) register or a Register File (RF), for example. Each read/write memory element in an integrated circuit is commonly tested to detect different types of faults by causing the memory element to execute a sequence of read and write operations unique to the particular type of memory to be tested. Among the faults sought to be detected during testing of a read/write memory element are retention faults. A retention fault occurs when a memory cell in the read/write memory element is unable to hold a value, such as a binary "1" or "0," over time.
The most common technique presently used to detect retention faults is to initiate execution by the memory element of its particular sequence of read and write operations. The sequence of operations is typically interrupted at each of two points for a predetermined interval (e.g., 100 milliseconds) to enable the retention faults, if any, to manifest themselves. The exact point at which the sequence of read and write operations should be interrupted depends on the nature of the memory element being tested.
The above-described retention fault testing scheme is not autonomous because the sequence of read and write operations must be manually interrupted to allow retention faults to manifest themselves. As indicated, the exact point at which the interruption should occur is dependent on the nature of the memory element being tested. Thus, the intervention of a test engineer during testing is generally required.
The above-described retention fault testing scheme is not unified because the sequence of read and write operations executed by each memory must be interrupted twice before another successive memory can execute its particular sequence of read and write operations. Accordingly, retention fault testing is thus delayed by the interruption interval allocated to each memory to allow for its retention faults (if any) to manifest themselves. Since the interruption (delay) interval is cumulative, the testing of a large number of memories in a single integrated circuit in succession thus becomes a lengthy process, leading to a long test time for the circuit.
Thus, there is a need for a retention fault detection technique which is both autonomous and unified.